The present invention relates to the thermal management of integrated circuits. In particular, the present invention relates to an integrated circuit stack comprising a plurality of integrated circuit layers comprising at least a first circuit layer electrically connected to a second circuit layer and at least one cooling layer arranged in a space between the first and second circuit layer.
The cooling of integrated circuits, of which increased performance expectations are placed, i.e. high-performance integrated circuits, is a particular challenge in a time of ever increasing circuit integration and performance demands. With increased computing requirements, so too do the processing speeds of integrated circuits and thus their clock frequencies increase, which leads to increased power consumption and, thus, heat dissipation. By a reduction in the size of individual components, such as transistors and memory cells, these components become faster. For electrical on-chip interconnects the opposite is the case. Due to the scaling effect the RC-time constant increases, which results in an increased signal flight time. This effect limits the chip performance and is called reverse scaling.
In known integrated circuits, most circuit components are arranged in what is essentially a single plane of a semiconductor material, often referred to as a die. Such a configuration allows increased efficiency in the cooling of the integrated circuit by means of a cooling arrangement mounted on the back surface of the integrated circuit. However, for the reduced length of signaling paths between individual circuit components, which translates in reduced signal flight times, and, also, to further aid chip integration, integrated circuit stacks are being developed, comprising multiple circuit layers stacked on top of each other. Cooling of such devices from the back side is particularly challenging as the dissipated heat flux of all the components accumulates and the conductive thermal resistance is increased with each additional component or circuit layer. This results in a higher temperature gradient in the chip stack.
An alternative cooling approach is the interlayer thermal management of such vertically integrated chip stacks. Such an approach is described in “Direct Liquid Cooling of a Stacked Multichip Module” by X. Y. Chen, K. C. Toh, and J. C. Chai. Therein, direct single-phase liquid cooling of a stacked multichip module is examined. A further integrated circuit stack is described in a paper titled “Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architectures” by J.-M. Koo, S. Im, L. Yang and K. E. Goodson. This paper studies three-dimensional circuit cooling by means of an integrated microchannel network. A further integrated circuit stack with interlayer cooling is known from a paper titled to “Process Integration of 3D Chip Stack with Vertical Interconnection” by K. Takahashi, Y. Taguchi, M. Tomisaka et al.
So far arrangements for cooling integrated circuit stacks with interlayer cooling are either concerned with the cooling of relatively low-performance integrated circuits, in particular memory modules, having a uniform structure and heat-dissipation or stacks with just peripheral electrical interconnects for lower bandwidth applications.
It remains a challenge to provide integrated circuit stacks for other kinds of applications, such as high-performance processors. It is a further challenge to provide a method for configuring integrated circuit stacks for higher-power operation and more efficient cooling. It is a further challenge to provide an integrated circuit stack and a method for its thermal management, which is applicable to smaller channel geometries, for example, of less than 300 μm gap between individual circuit layers.